This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...

The design of a closed-loop switch-mode power supply creates a path between the variable a designer wants to monitor and the control pin of the designer's converter. This control pin can be the peak ...

In Part 1, we reviewed the low frequency behavior of the HCNR200 circuit, and obtained the stability conditions by analyzing its open-loop transfer function. In this session, we still study the system ...

Some brief theory and typical measurements of phase noise. How to produce the lowest phase noise at a PLL output. A standard design procedure for a typical Type 2, second-order loop. As stated in ...