Design-Reuse

ChipX Simplifies DDR2 Design With Industry Standard DDR PHY Interface v2.0

March 12, 2008 -- ChipX, Inc., a leading developer of mixed-signal ASICs offering the industry's broadest array of value-added solutions, today announced that it has adopted the industry standard DDR ...
マイナビニュース

Cadence、28nmプロセスで実証されたDDR4設計IPソリューションを発表

Cadence Design Systemsは9月4日(米国時間)、DDR4 SDRAM PHYおよびメモリコントローラ用設計IP製品が、TSMCの28HPMおよび28HPプロセスで実証されたと発表した。 今回、DDR4規格の暫定仕様に基づいた複数バージョンのDDR PHYとコントローラIPを28nmプロセス上にて実装した ...
Design-Reuse

DDR PHY Interface Specification to be Unveiled Next Week at MemCon

ARM, Denali, Intel, Rambus, Samsung, and Synopsys team on specification to address development challenges for DDR-DRAM memory systems PALO ALTO, Calif. -- Sept. 6, 2006 -- Denali Software, Inc., today ...
Yahoo Finance

Faraday Delivers DDR/LPDDR Combo PHY IP Solutions on UMC’s 22ULP and 14FFC

HSINCHU, Taiwan, July 22, 2025--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design and IP provider, today announced the availability of its DDR/LPDDR combo PHY, ...
Business Wire

Faraday Delivers DDR/LPDDR Combo PHY IP Solutions on UMC’s 22ULP and 14FFC

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design and IP provider, today announced the availability of its DDR/LPDDR combo PHY, supporting from 3 rd ...